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System Electrothermal Transient Analysis of a High Current (40A) Synchronous Step Down Converter

In this paper, we detailed the system electrothermal transient co-design modeling and silicon validation effort that led to the industry’s first highly efficient, highest power density (40A) synchronous step-down converter.

Sigrity X – Redefining Signal and Power Integrity

This white paper highlights the features in Cadence® Sigrity™ X signal and power integrity (SI/PI) solutions for system-level SI and PI analysis that enable designers to cut the number of design respins and meet short time-to-market windows with confidence.

Serial Link Engineering: A Novel Jitter/Noise Metric to Qualify Channel Components

This whitepaper will discuss a novel eye-area based normalized jitter and noise metric for serial link analysis.

Rocket EMS Shares First Pass Design Success Tips

Learn a systematic approach to change the often LOSE-LOSE relationship between a contract manufacturer (CM) and startup to a WIN-WIN.

Rigid Flex: DFM and Design Rule Considerations

This paper discusses some of the key challenges to address and also introduces a new PCB design approach that enhances productivity through in-design inter-layer checks required to ensure correct-by-construction design.

How to Define and Add Interposer to Your Die Stack

In this document, you will learn how to create an interposer library object and place an instance of that definition into your SiP substrate design.

How to Create a Symbol from SiP and Import into Virtuoso

This document will help designers use chips and connectivity from SiP Layout to create a symbol in Virtuoso, saving time.

How to Convert a UPD Package Substrate for Use with APD and SiP Layout

This document describes the procedure to import UPD spd2 format files in Cadence Allegro Package Designer (APD) or SiP Layout tools and creating your APD/SiP Layout libraries based on imported data.

Export DIE abstract (XDA) from Virtuoso for use with SiP Layout and OrbitIO

After going through this application note you will be able to export DIE data from IC (Virtuoso) to Cadence Chip packaging tool (SiP and OrbitIO).

ECO Process for Cadence SiP

This application note will go through the flow and process needed to take a BGA with 420 pins and replace it with a component with 421 pins.

Early Die Bump Planning using SiP Layout with EDIS

Learn the process for early IC bump planning and data exchange based on DEF and die abstract using the SiP Layout and Encounter Digital Implementation System (EDIS) environments.