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Home > EMA Resources > Videos > Setting up Timing Budget and Analysis Options for SPBS: Part 2
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Setting up Timing Budget and Analysis Options for SPBS: Part 2

Learn how to configure simulation parameters and set analysis options for a DDR4 simulation in Sigrity.
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    VIDEO

    Setting up Timing Budget and Analysis Options for SPBS: Part 2

    Duration: 00:05:51

    A simple parallel bus system (SPBS) is one in which data is transferred between components using multiple parallel communication lines, such as DDR4 and DDR5. Sigrity allows you to run circuit or channel simulation for a parallel bus system. In this video, we’ll set analysis options for DDR4 SPBS circuit simulation (part 7 of 10). Throughout this video, you will:

    • Open a project in Topology Explorer
    • Configure Simulation Parameters
    • Configure a Bus Simulation
    • Add I/O Models
    • Save a Topology

    Learn more about how Sigrity can help you simulate and verify interface operation and follow along with the demo files here.

    This video is part 7 of a 10-part series:

    1. Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 1
    2. Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 2
    3. Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 3
    4. Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 4
    5. Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 5
    6. Setting up Timing Budget and Analysis Options for SPBS: Part 1
    7. Setting up Timing Budget and Analysis Options for SPBS: Part 2
    8. Setting up Timing Budget and Analysis Options for SPBS: Part 3
    9. Performing Circuit Simulation and Analysis on SPBS: Part 1
    10. Performing Circuit Simulation and Analysis on SPBS: Part 2

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