A simple parallel bus system (SPBS) is one in which data is transferred between components using multiple parallel communication lines, such as DDR4 and DDR5. With Sigrity Topology Explorer, we can perform circuit simulation and analysis of Simple Parallel Bus Systems (part 10 of 10). In the final video of this series, we’ll run circuit simulation of DDR4 SPBS using System SI and analyze simulation results, generated 2D plots, and reports. You will learn:
- How to load a project file in Topology Explorer 22.1
- How to plot and analyze results
- Analyze results against compliance standards
- Analyze jitter
- Generate a simulation report
- Save the topology
Learn more about how Sigrity can help you simulate and verify interface operation and follow along with the demo files here.
This video is part 10 of a 10-part series:
- Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 1
- Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 2
- Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 3
- Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 4
- Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 5
- Setting up Timing Budget and Analysis Options for SPBS: Part 1
- Setting up Timing Budget and Analysis Options for SPBS: Part 2
- Setting up Timing Budget and Analysis Options for SPBS: Part 3
- Performing Circuit Simulation and Analysis on SPBS: Part 1
- Performing Circuit Simulation and Analysis on SPBS: Part 2
