A simple parallel bus system (SPBS) is one in which data is transferred between components using multiple parallel communication lines, such as DDR4 and DDR5. Topology Explorer provides two separate workflows for analyzing Parallel Bus and Serial Link interfaces. In this series of videos, we will learn how to model, simulate, and analyze a Simple Parallel Bus System. In this video, you will learn:
- How to open an existing project
- How to generate a W-Element Block
- How to Define T-Line properties
- How to adjust traces for impedance
Learn more about how Sigrity can help you simulate and verify interface operation and follow along with the demo files here.
This video is part 3 of a 10-part series:
- Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 1
- Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 2
- Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 3
- Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 4
- Modeling, Simulation, and Analysis of a Simple Parallel Bus System: Part 5
- Setting up Timing Budget and Analysis Options for SPBS: Part 1
- Setting up Timing Budget and Analysis Options for SPBS: Part 2
- Setting up Timing Budget and Analysis Options for SPBS: Part 3
- Performing Circuit Simulation and Analysis on SPBS: Part 1
- Performing Circuit Simulation and Analysis on SPBS: Part 2
