Modeling designs help engineers verify whether their circuit will function as intended. Modeling programs simulate circuit behavior under different conditions and in accordance with the design requirements, allowing engineers to better plan and build circuits.
Typically, to model components, generic models are used, which produce inaccurate and unrealistic simulations based on ideal conditions. This can cause functionality issues to go undetected until far later in the design process. To confidently simulate digital designs, create an SR latch SPICE model using specifications from a manufacturer’s datasheet.
What is an SR Latch?
A Set-Reset (SR) Latch is a basic type of digital memory that stores a single bit of data. It is made up of NAND or NOR and is considered a bistable circuit because it has two stable states: one for storing a logic 1 and another for storing a logic 0.
An SR latch is a level-sensitive single-bit storage device where S and R stand for set and reset respectively. S=1 and R=1 is a forbidden state.
SR latches can contain an additional set and reset pin. The set and reset pins work as preset and clear to initialize the latch.
The SR Latch contains the following inputs and outputs:
- Set (S): The input signal used to set the output to 1.
- Reset (R): The input signal used to reset the output to 0.
- Primary Output (Q): Primary output reflecting the stored bit (either 1 or 0).
- Complementary Output (Q-bar): The inverse of Q.
The following truth table displays the functionality of an SR Latch:
What is Needed to Model an SR Latch?
SR Latches are typically used for memory elements, basic sequential circuits forming the foundation of more complex storage devices, and control systems. To realistically simulate digital circuit functionality and create an SR latch SPICE model for simulation, there are four items that must be defined:
Logic Parameters
For accurate behavioral representation, the initial condition of the SR Latch must be defined.
Timing Characteristics
Timing is critical to digital design operation and performance. Consider the propagation delay for the SR Latch device.
DC Electrical Characteristics
The DC electrical characteristics define the operating conditions for the SR latch. This includes:
- The maximum output voltages during high-level and low-level operation
- The voltage levels or thresholds that control the switch from high-level operation to low-level operation
- Hysteresis is often defined for these devices to provide a cushion, ensuring accurate switching between low-level and high-level states even with noisy input signals. It is typically provided by device manufacturers on the device datasheet as VH; however, if not provided it can be calculated by the following equation:
VH = VT+ – VT-
The input is HIGH when it rises above Threshold + (Hysteresis Width/2).
The input is LOW when it falls below Threshold – (Hysteresis Width/2).
Device Resistance
Input and output resistance of the device is critical to the operation and necessary to create an accurate model representation. If this parameter is not provided on the device datasheet, it can be calculated with Ohm’s law.
- Input Resistance (RIN)
Use the maximum input voltage (VIN) and maximum leakage current (commonly IIN or Il) to calculate the input resistance.
- Output Resistance (ROUT)
Use the maximum output voltage (VOH or VOL) and the maximum output current (IOH or IOL) to calculate the output resistance.
Once this information is obtained and calculated, these values must be incorporated into the SPICE simulation model which can be achieved by manually creating or editing a text file. Keep in mind if the SR latch created does not produce the intended outcome and a decision is made to change components, values will need to be re-calculated and edited manually. This manual process to produce an accurate SR latch SPICE model is time consuming and increases the likelihood of errors; however, the PSpice Modeling App provides a fast, easily configurable, and fully integrated method to create SR latch SPICE models for simulation. Â
Creating an SR Latch SPICE Model with the PSpice Modeling App
The SR latch modeling application quickly creates SR latch SPICE models with a wizard-based approach. To create SR latch models, users can easily input the characteristics, defined by manufacturers, directly into predefined parameters:Â Â
Initial Condition
Define the initial condition of the latch as 0 or 1.
Propagation Delay
Define the time from when the input on a pin changes state until the output changes in seconds. This is typically identified as tpd, tpLH, or tpHL on device datasheets.
Threshold (TH)
Define the voltage level (V) that indicates a switch between high-level and low-level operation.
Hysteresis Width
Hysteresis is the difference between the positive input threshold voltage and the negative input threshold voltage. It is typically provided on the device datasheet as VH.
Output Resistance (ROUT)
Specify the resistance of the output pin in ohms.
Input Resistance (RIN)
Specify the input resistance at each input pin of the latch in ohms.
Max High Voltage
Define the output high voltage. This is typically defined on device datasheets as VOH.
Max Low Voltage
Define the output low voltage. This is typically defined on device datasheets as VOL.
Using the inputted information above, the PSpice Modeling App generates a schematic symbol and automatically associates the newly created SR latch SPICE model without leaving the OrCAD Capture environment. The PSpice Modeling App also automatically manages the simulation profile configuration, eliminating any library set up for simulation.
Be sure to check out additional SPICE model explanations in this series and get the step-by-step instructions for creating an SR Latch SPICE model in PSpice here.
