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PCIe Gen 6: PCB Design Essentials

PCIe connector detail on a high-end graphics card with metal backplate heatsink

PCIe (Peripheral Component Interconnect Express) Generation 6 (PCIe 6.0) is the latest iteration of the PCIe standard–PCIe 7 is in the works, but not scheduled for release until 2025–, designed to boost data transfer speeds and efficiency for high-performance computing, data centers, and networking applications. To leverage the capabilities of PCIe Gen 6 applications, your PCB design needs to handle the high data rates and stringent requirements of the PCIe protocol. Here are some best practices for PCB design.

PCIe Gen 6: PCB Design Essentials

Aspect

Best Practice

Signal Integrity

✔ Use differential pairs with tight coupling to minimize noise and crosstalk.

✔ Maintain consistent trace impedance to match the characteristic impedance of PCIe Gen 6 (typically 85-100 ohms).

✔ Implement proper termination to avoid signal reflections.

✔ Use short and direct routing for high-speed signal paths to reduce latency and signal degradation.

Power Integrity

✔ Ensure a robust power delivery network (PDN) with low impedance across a wide frequency range.

✔ Use multiple ground planes to provide a stable reference and reduce electromagnetic interference (EMI).

✔ Implement decoupling capacitors close to the power pins of PCIe Gen 6 devices to filter high-frequency noise.

Layer Stackup

✔ Design a multilayer PCB with dedicated power, ground, and routing layers to improve signal integrity.

✔ Ensure proper layer spacing to control impedance and reduce EMI.

Via Management

✔ Minimize the use of vias in high-speed signal paths, as they can introduce impedance discontinuities.

✔ Use back drilling or blind/buried vias to reduce via stub lengths and improve signal integrity.

Trace Length Matching

✔ Ensure differential pair trace lengths are matched to minimize skew and ensure timing alignment.

✔ Keep trace lengths as short as possible to reduce propagation delay and signal loss.

Routing Techniques

✔ Avoid sharp bends in high-speed traces; use 45-degree angles or curved traces to reduce signal reflections.

✔ Route differential pairs together with equal length and spacing to maintain the differential impedance.

Grounding

✔ Implement a solid ground plane beneath high-speed signal traces to provide a low-inductance return path.

✔ Connect ground planes with vias to ensure a low-impedance path for return currents.

Connector Placement

✔ Place PCIe Gen 6 connectors close to the board’s edge to reduce trace lengths and improve signal integrity.

✔ Ensure proper mechanical support for connectors to maintain signal integrity under mechanical stress.

Thermal Management

✔ Implement adequate cooling solutions (e.g., heatsinks, fans) to manage heat dissipation from high-speed PCIe Gen 6 devices.

✔ Use thermal vias and copper pours to enhance heat dissipation through the PCB.

Simulation and Testing

✔ Perform signal integrity simulations to validate the design before fabrication.

✔ Conduct pre-layout and post-layout simulations to identify and mitigate potential issues.

✔ Perform thorough testing and validation of the PCB to ensure compliance with PCIe Gen 6 specifications.
These best practices help ensure that your PCB design can handle the high data rates and stringent requirements of the PCIe 6.0 protocol, resulting in reliable and efficient performance. The best way to ensure these essentials are incorporated and that your board will meet the requirements for successful operation is to perform compliance testing during PCB design.  For detailed information on compliance testing, see the eBook: Engineer’s Guide to PCIe: How To Achieve PCIe Compliance Upfront.

PCIe Gen 6 Features and Applications

PCIe Gen 6 doubles the data transfer rate and lane speed of PCIe Gen 5, while introducing error correction for enhanced reliability at these higher speeds. Both versions remain backward compatible with previous generations. To better understand the features enabled by PCIe Gen 6, let’s compare them to PCIe Gen 5.

PCIe Gen 5 vs PCIe Gen 6

Feature

PCIe 5.0

PCIe 6.0

Data Rate

32 gigatransfers per second (GT/s) per lane

64 GT/s per lane

Maximum Bandwidth

128 gigabytes per second (GB/s) (x16 configuration, bidirectional)

256 GB/s (x16 configuration, bidirectional)

Encoding Scheme

NRZ (non-return-to-zero)

PAM-4 (pulse amplitude modulation with 4 levels)

Forward Error Correction (FEC)

No

Yes, low-latency FEC

Flow Control Unit (Flit) Mode

No

Yes, new flit-based encoding

Latency

Low

Lower due to improved protocols and FEC

Power Efficiency

Improved over previous generations

Further improved efficiency

Backward Compatibility

Compatible with PCIe 4.0, 3.0, 2.0, and 1.0

Compatible with PCIe 5.0, 4.0, 3.0, 2.0, and 1.0

Channel Reach

Similar to PCIe 4.0

Improved equalization techniques for longer reach

Signal Integrity Requirements

High

Higher due to increased data rates
Based on these features, here are some common PCIe Gen 6 applications:
  • Data Centers: Increased data transfer speeds and efficiency make PCIe Gen 6 ideal for data center applications, where fast and reliable data access is crucial.
  • AI and Machine Learning: PCIe Gen 6’s high bandwidth and low latency support the demanding data requirements of AI and machine learning workloads.
  • High-Performance Computing: PCIe Gen 6’s enhanced performance benefits high-performance computing applications, such as scientific simulations, financial modeling, and other data-intensive tasks.
  • Networking: PCIe Gen 6 improves the performance of network interface cards (NICs) and other networking equipment, supporting faster and more efficient data transmission.
PCIe Gen 6 represents a significant advancement in the PCIe standard, providing higher data rates, improved efficiency, and better error correction mechanisms. It is poised to support the next generation of high-performance computing, data centers, and networking applications. Following PCB design best practices is essential to leveraging these advanced capabilities. For the most efficient design process and PCB development optimization, you should use industry-leading PCB design and development software. In many cases, this requires the integration of advanced simulation and development tools with your EDA program. For PCIe Gen 6 designs, Sigrity provides the best platform for achieving pre-manufacturing compliance assurance for PCBs that deploy this high-speed data transfer protocol. 
EMA Design Automation is a leading provider of the resources that engineers rely on to accelerate innovation. We provide solutions that include PCB design and analysis packages, custom integration software, engineering expertise, and a comprehensive academy of learning and training materials, which enable you to create more efficiently. For more information on PCIe Gen 6 PCB design essentials and how we can help you or your team innovate faster, contact us.
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