Essential FPGA PCB Design Guide

Field programmable gate arrays (FPGAs) bundle extensive functionality in a high-density pinout package, making them highly suitable for many applications. However, proper performance requires not only important PCB design rules be followed, but also design practices that meet the unique challenges of these components. This FPGA PCB design guide breaks down the broad approach to circuit design and layout to ensure optimal performance.

ADDITIONAL FPGA PCB DESIGN GUIDELINES
Switching Signal Noise (SSN)	Keep power and ground planes close (the higher the capacitance, the lower the inductance) Keep power and ground nets close to ICs to reduce inductance Keep differential signals tightly coupled Reduce driver speed if maximum is not necessary
Decoupling	Keep the lowest-value capacitors closest to IC power/ground pins If via-in-pad is possible, run a trace from the IC power/ground pins directly to the capacitor
Stackup	Avoid split-plane design, if possible If split-plane design is necessary, no trace must cross the gap between planes

FPGA PCB Design Guide Breakdown

Avoiding Discontinuities

Continuity generally refers to the direct connection between signals defined by the netlist. The unrouted connections that appear in a design rule check are not the focus, but rather impedance discontinuities. Any signal traversing a physical medium can experience impedance discontinuities (think routing over split gaps in reference planes, changes in substrate materials, etc.) and are either inductive or capacitive relative to the originating signal characteristics:

• Inductive discontinuities appear over-terminated relative to the driver.
• Capacitive discontinuities appear under-terminated relative to the driver. This type of discontinuity can occur when components are in line with the transmission.

Additionally, discontinuities can occur due to the geometry of the transmission path. Via transitions and right-angle corners (in reality, vias are right-angle corners in and out of the plane) add capacitive discontinuity to the transmission line. For the via, the discontinuity is due to the parallel capacitance formed by the via pads on successive layers (meaning the effect becomes more pronounced on thicker boards with higher layer counts) and stubs; alternatively, right-angle corners create a thicker transmission line width at the turn. In general, right-angle corners are unnecessary, and designers often forego them in favor of mitered-45-degree angles for aesthetic purposes. Vias are a necessary routing tool for HDI boards, but designers can limit their discontinuity potential by following best practices:

• As a first rule of thumb, determine if a via is necessary. Some areas of the board (like under the BGA) require vias for signal breakout. However, careful placement and routing can eliminate unnecessary vias, with the added benefit of reducing cost/fabrication defect vectors.
• Speaking of via breakout, microvias (i.e., blind vias for BGAs) exhibit less of a discontinuity than traditional vias. While they will be more expensive, they are indispensable for HDI boards.
• When routing differential pairs, place a ground via for each via transition equidistant from the transmission line vias. This placement will keep return loops small and limit EMI.
• Consider backdrilling to remove via stubs. This process is optional but can remove unnecessary transmission line length from the via barrels that cause reflections.

Termination

Signals need termination to ensure the correct transfer from driver to receiver in the transmission line and prevent reflections. Placement of the terminating resistors and their topology is key:

• Series termination is on the driver-side of the transmission line and is suitable for clock signals only. The terminating resistor acts as a voltage divider for the signal originating at the driver before reflecting from the terminating resistor to the receiver for the full amplitude.
• Parallel termination can be on both ends or only the receiver side of the transmission line. The terminating resistors should be as close to the driver or receiver as possible.

Similar to decoupling capacitors, position the smallest value resistors closest to the driver/receiver end of the transmission line.

Trace Layout

Accommodating an HDI layout requires tightly coupled traces. Tight coupling reduces the space between traces for greater routing efficiency, but designers must be mindful of crosstalk. Traces should also be as wide as possible to reduce resistive losses during transmission. The 3W rule is an excellent rule of thumb for balancing trace thickness and gaps: measured trace center-to-center, the gap between traces should be at least three times the thickness of the traces. Consider some additional trace guidelines:

• Keep skew to a minimum (i.e., zero) for differential pairs to prevent timing mismatches that undermine the common-mode noise cancellation. Although there will be an impedance mismatch where the traces separate to add length to the shorter line, this effect is negligible for all but the shortest differential pair trace lengths.
• Avoid interplanar coupling/crosstalk by having traces cross perpendicular on adjacent signal layers.

EMA Accelerates PCB Designs

FPGA PCB design guides focus on the broad strokes of board development and layout, but individual design intent may supersede these general rules. If you’re looking for support on your next FPGA-enabled device, EMA is here to help. With library support, next-generation layout software, training courses, and additional resources, EMA can streamline electronics development to enable faster design turnaround and better performance.