Aldec Active-HDL: Evaluation Request

Aldec® Active-HDL™ is the digital design entry and simulation tool with all the capabilities necessary for an FPGA designer to successfully develop and validate their FPGAs. Designers using Active-HDL have a steamlined FPGA design environment that reduces simulation and verification time all within a price that fits in their budget. Simply complete the form below to request an evaluation version of this software.

Contact Information

*First Name:   *Last Name:   *Company Name:   *Street Address   *City:   *State/Province: *Zip:   Country:   USA Canada *Phone   Ext. Fax   *Email Address   *Confirm Email Address   Website URL:   *Job Title:         Evaluation License:   Please send me a free, fully functional temporary license Your MAC Address/Host ID:    Instructions       What FPGAs interest you?   Actel™ Altera® Lattice® Quicklogic® Xlinx®       Which HDLs interest you?   Assertions OVL/PSL/SVA SystemC/C/C++ SystemVerilog Verilog VHDL       Are you interested in any specialty solutions?   FPGA/PCB Co-Design Code Coverage Design Rule Checking (LINT) DO-254 compliance Matlab/Simulink co-simulation       Do you have a timeline for purchasing?   = select = A. Immediately B. Within 90 days C. 90 days to 6 months D. Later than six months       How did you hear about us?   Select A Source EMA Newsletter EMA website Email Friend or colleague Internet Search Tradeshow or event Other (Complete 'Other' field) Other: