Active-HDL

Comprehensive FPGA design simulation and verification environment

Features		Designer Edition	Plus Edition (PE)	Expert Edition (EE)
	Active-HDL
Design Entry
HDL, Text, Block Diagram and State Machine Editor		•	•	•
Language assistant with templates and auto-complete		•	•	•
Hierarchy Viewer with Configurations Support		•	•	•
Macro, Tcl/TK, Perl script support		•	•	•
Pre-compiled FPGA Vendor Libraries		•	•	•
Code2Graphics™ Converter			•	•
Legacy Schematic Design Import and Symbol Import/Export			•	•
Supported Languages
Single or Mixed Language Design Support		Mixed Only	•	•
VHDL IEEE 1076 (1987, 1993, 2002 and 2008)		•	•	•
Verilog® HDL IEEE 1364 (1995, 2001 and 2005)		•	•	•
SystemVerilog IEEE 1800 (Design)		•	•	•
Verilog Programming Language Interface (PLI/VPI)		•	•	•
VHDL Programming Language Interface (VHPI)			•	•
EDIF 2 0 0			•	•
Language Interface Wizard (PLI/VPI/VHPI/DPI)			•	•
SystemVerilog IEEE DPI w/Wizard			•	•
SystemC™ 2.2 IEEE 1666/OSCI 2.2/TLM 2.0			Option	•
Code Generation Tools
IP Core Component Generator			•	•
VHPI/PLI/VPI, SystemC Transactor and New File Wizards			•	•
Testbench Generation from Waveforms			•	•
Testbench Generation from State Diagram			•	•
Project Management
Design Flow Manager for All FPGA Vendors		•	•	•
Revision Control Interface		•	•	•
Workspace and Design Archiving		•	•	•
Support for Multi-Design Workspace			•	•
Simulation/Verification
Simulation Performance		Baseline (2X over FPGA vendor supplied simulators)	3X Baseline	Verilog 6X Baseline VHDL 4.5X Baseline
Simulation Model Protection		•	•	•
Verilog 2005 IEEE Encryption		•	•	•
VHDL 2008 IEEE Encryption		•	•	•
Value Change Dump (VCD and Extended VCD) Support		•	•	•
Batch Mode Simulation/Regression (VSimSA)			•	•
Profiler (Performance Metrics)			Option	•
Verilog RTL & Gate Performance Optimization				•
VHDL RTL & VITAL Performance Optimization				•
HDL Debug and Analysis
Interactive Code Execution Tracing		•	•	•
Advanced Breakpoint Management		•	•	•
Signal Probes on Graphics/Animation of Graphics		•	•	•
Memory Viewer		•	•	•
FSM Debug		•	•	•
Waveform Viewer (AWF and ASDB)		•	•	•
Multiple Waveform Windows		•	•	•
Waveform Stimulator		•	•	•
Assertions Debugging			Option	Option
Waveform Comparison			•	•
Waveform Editor			•	•
Post Simulation Debug			•	•
C++ Debugger			•	•
Signal Agent (VHDL and Mixed Only)			•	•
X-Trace			Option	•
Advanced Dataflow			Option	•
Extra Standalone Accelerated Waveform Viewer (ASDB)			Option	Option
Coverage Tools Bundle
Statement, Branch, Expression, Conditional and Toggle Coverage			Option	•
Functional Coverage in Assertions/Code Coverage			Option	Option
VHDL Path Coverage				•
Lint - Design Rule Checking
ALINT™ with Basic Rule Library			Option	•
STARC® Verilog or VHDL Rule Library			Option	Option
DO-254 Verilog or VHDL Rule Library			Option	Option
External Simulation Interfaces
Xilinx® SecureIP Support		•	Option VHDL Only	•
Synopsys SmartModels®, SWIFT™ Interface and LMTV			Option	•
SpringSoft® Verdi™ PSD mode Interface			Option	•
Co-simulation and C-Synthesis
Simulink® Co-simulation			•	•
MATLAB® Co-simulation			Option	•
Assertions Bundle
PSL IEEE 1850, SystemVerilog IEEE 1800, OpenVera Assertions			Option	Option
Documentation
Export to PDF/HTML/Bitmap Graphics			•	•
Advanced Export to PDF (Vector Graphics)			•	•
Specialty Solutions
PCB Interface (Automated FPGA I/O synchronization)			•	•
SFM (Server Farm)			Option	Option
Licensing
Node Locked License		•	•	•
Floating License		•	•	•
One Year Time Based License		•	•	•
Perpetual License			•	•
Supported Platforms
Windows® 7/Vista/XP/2003		•	•	•

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